OpenAI and Broadcom unveil LLM-optimized inference chip Jalapeño
OpenAI and Broadcom announced Jalapeño, OpenAI‘s first custom inference chip, built explicitly for LLM workloads rather than repurposed from earlier AI accelerators. The article exposes the tension between general-purpose AI hardware and the specialized demands of modern LLM inference: current state-of-the-art accelerators leave significant performance on the table because they were designed for earlier model architectures. OpenAI claims early testing shows Jalapeño delivers substantially better performance per watt than existing chips, with realized utilization much closer to theoretical peak, by optimizing the entire architecture around the kernels, memory movement, networking, and serving patterns that matter most for frontier models like GPT-5.3-Codex-Spark, which is already running on engineering samples in the lab.
The chip went from initial design to manufacturing tape-out in just nine months, which the companies believe is the fastest ASIC development cycle ever achieved in high-performance semiconductors. That speed came from deep software-hardware co-development with OpenAI‘s engineering teams, Broadcom‘s silicon implementation expertise, and the novel use of OpenAI‘s own models to accelerate parts of the chip design and optimization process. The architecture reduces data movement and balances compute, memory, and networking resources—with Broadcom‘s Tomahawk networking silicon playing a key role. Deployment at gigawatt scale with data center partners including Microsoft is planned to begin in 2026, as part of a multi-generation compute platform.
The serious takeaway for builders is that OpenAI is pursuing a full-stack infrastructure strategy, owning chip architecture, kernels, memory systems, networking, scheduling, and deployment. This creates a tight feedback loop: better infrastructure drives compute efficiency, which enables better training and serving, which powers more capable models, which become better products, which drive more revenue to reinvest in the next infrastructure generation. For engineers evaluating inference hardware, Jalapeño signals that the industry is moving toward purpose-built LLM accelerators where the performance gains come from deep co-design between model developers and silicon architects. The nine-month tape-out timeline also suggests that AI-assisted chip design could meaningfully compress hardware development cycles, potentially lowering the cost and barriers to custom silicon for AI workloads.
